View CRD4202-2_1112845.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CRD4202-2
AC '97 Six Channel CNR Audio Reference Design with PLL
Features
Phase Locked Loop (PLL) Codec Operation Six Channel Analog Audio Outputs Headphone Sense using GPIO CS4202 codec and two CS4334 DACs 20-bit D to A conversion (DAC) 18-bit A to D conversion (ADC) S/PDIF (IEC-958) optical digital output Complete suite of Analog I/O connections:
- Line, Mic, CD, Video, Modem, and Aux Inputs - Modem, Headphone, Line Front, Line Rear and Line Center/Sub-Woofer Outputs
Description
The CRD4202-2 reference design eliminates the cost of the 24.567 MHz crystal by operating the CS4202 in Phase Locked Loop (PLL) mode. This reference design also features six channel analog audio outputs, an optical S/PDIF digital output, and Communication and Networking Riser (CNR) interface. This design uses the CS4202 audio codec which has several advanced features including a built-in headphone amplifier, simultaneous six channel analog and S/PDIF optical digital output, GPIO for headphone detection, and up to 30 dB of internal microphone boost. The CRD4202-2 reference design is available by ordering the CMK4202-2 manufacturing kit. This kit includes the CRD4202-2 board, a full set of schematic design files (OrCAD(R) format), PCB job files (PADS(R) ASCII), PCB artwork files, and bill of materials. This reference design offers significant cost savings over competing solutions and can be easily modified to meet your specific design goals. ORDERING INFO CMK4202-2 (Manufacturing Kit)
2-layer low cost PC board Complies with Intel (R) AC '97 revision 2.2 Exceeds Microsoft's(R) PC 2001 audio performance requirements.
Microphone Input Line Input Line Output Headphone Output Rear Channel Output Center / Sub-Woofer Output S/PDIF Digital Optical Output
MIC IN INT MODEM LINE IN LINE OUT HEADPH OUT SURR OUT CNT/LFE OUT CD IN VIDEO IN AUX IN
Cirrus Logic CRD4202-1
CS4202
S/PDIF OUT
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2002 (All Rights Reserved)
MAR `02 DS549RD1B1 1
(c)
CRD4202-2
TABLE OF CONTENTS
1. GENERAL INFORMATION ...................................................................................3 2. SCHEMATIC DESCRIPTION ................................................................................3 2.1 CS4202 Audio Codec .................................................................................3 2.2 Analog Inputs ..............................................................................................3 2.3 Center, LFE, and Surround Outputs ...........................................................4 2.4 Front Channel and Headphone Outputs .....................................................4 2.5 S/PDIF Optical Output ................................................................................4 2.6 CNR Connector and EEPROM ...................................................................4 2.7 Auto Demotion Circuit .................................................................................4 2.8 Phase Locked Loop ....................................................................................4 2.9 Component Selection .................................................................................5 2.10 EMI Components ......................................................................................5 3. GROUNDING AND LAYOUT ................................................................................5 3.1 Partitioned Voltage and Ground Planes .....................................................5 3.2 AC-Link .......................................................................................................5 3.3 CS4202 Layout Notes .................................................................................5 4. REFERENCES .......................................................................................................6 4.1 ADDENDUM ...............................................................................................6 5. BILL OF MATERIALS .........................................................................................21
LIST OF FIGURES
Figure 1. Block Diagram ....................................................................................................7 Figure 2. CS4202 Audio Codec .........................................................................................8 Figure 3. Analog Inputs ......................................................................................................9 Figure 4. Center Channel, Surround, and Sub-Woofer Outputs ......................................10 Figure 5. Front Channel and Headphone Sense Output .................................................11 Figure 6. S/PDIF Optical Output ......................................................................................12 Figure 7. CNR Connector ................................................................................................13 Figure 8. Phase Locked Loop ..........................................................................................14 Figure 9. Auto Demotion and Serial Buffers ....................................................................15 Figure 10. PCB Layout: Top Assembly Drawing ..............................................................16 Figure 11. PCB Layout: Top Layer ..................................................................................17 Figure 12. PCB Layout: Bottom Layer .............................................................................18 Figure 13. PCB Layout: Drill Drawing ..............................................................................19 Figure 14. PCB Layout: Top Silkscreen ...........................................................................20
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/
Microsoft, Windows 95, Windows 98 and Windows Millennium and WHQL is registered trademark of Microsoft. CrystalClear is a trademark of Cirrus Logic, Inc. Intel is a registered trademark of Intel Corporation. OrCAD is a registered trademark of OrCAD, Inc. PADS is a registered trademark of, PADS Software, Inc. Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
2
DS549RD1B1
CRD4202-2
1. GENERAL INFORMATION
The CRD4202-2 CNR reference design features six channel CD quality analog and S/PDIF digital audio outputs. The card includes the CS4202 AC '97 audio codec operating in PLL mode, and two CS4334 24-bit serial stereo DACs. This combination gives the CRD4202-2 a rich feature set and industry leading audio performance. The CS4202 audio codec includes a stereo 20-bit DAC, a stereo 18-bit ADC, and a very flexible analog audio mixer. The serial data outputs are paired with two CS4334 DACs to provide four additional channels of analog audio. The CS4202 also features three stereo pairs of line level analog inputs, a microphone input, and a stereo pseudo-differential CD input. The input signals can be routed to the ADC for recording or mixed together for recording and direct playback. The CS4202 has internal registers that are used to control its various features such as volume levels, audio muting, and signal routing. The CS4202 maintains high audio quality and exceeds the Microsoft(R) PC 2001 audio performance specifications. The CS4202 audio codec communicates to the audio controller across the CNR interface using the AC-Link. The AC-Link is a 5-wire serial digital interface that transfers digital audio data and GPIO control/status data between the two devices, sends commands from the audio controller to the codec, and provides codec status information to the controller. For additional information on the AC-Link, see the Intel(R) AC '97 revision 2.2 specification.
2.1
CS4202 Audio Codec
The CS4202 audio codec is shown in Figure 2. The analog input signals to the CS4202 originate from the inputs in Figure 3, while the analog outputs are shown in Figure 4 and Figure 5. AFLT1 and AFLT2 (pins 29, 30) require 1000 pF NPO/C0G capacitors connected to analog ground. These capacitors provide a single pole lowpass filter to the inputs of the CS4202 ADC. No other input filtering is required. The AC-Link may require series termination resistors to prevent reflections. These are normally placed as close as possible to the transmitting end of the AC-Link signal. The CS4202 SDATA_IN (pin 8) and BIT_CLK (pin 6) outputs have 47 series termination resistors. The CS4202 is powered by separate analog and digital power supplies, each with their own respective grounds. The AGND symbols refer to analog ground and DGND symbols refer to digital ground. For best results, connect the grounds together at a single point with a 0.050 inch trace underneath the CS4202. Each power pin requires an individual decoupling capacitor. These decoupling capacitors are placed as close as possible to their respective pins. The CS4202 audio codec uses a 0.1 F ceramic capacitor for each of the +3.3 V digital and +5 V analog supply pins.
2.2
Analog Inputs
2. SCHEMATIC DESCRIPTION
The block diagram in Figure 1 illustrates the interconnections between the schematic pages found at the end of this document. Sections 2.1 through 2.8 describe the circuitry contained in these schematics.
The LINE_IN, VIDEO_IN, and AUX_IN stereo inputs shown in Figure 3 are AC-coupled to the CS4202 codec with 1 F capacitors to minimize low frequency roll-off. The pull down resistors are recommended to prevent noise from coupling to the analog inputs when they are not in use. Locations for 6 dB dividers were provided for 2.0 Vrms input compatibility, but are not required for PC 2001 compliance. The microphone input is AC-coupled with a 1 F capacitor to minimize low frequency roll-off. The
DS549RD1B1
3
CRD4202-2
microphone circuit provides low voltage phantom power for electret microphones. Phantom power is derived from the +5 V analog supply and provides a maximum of 4.2 V under no load and a minimum of 2.0 V under a 0.8 mA load, as required by PC 2001 specifications. The CS4202 features a pseudo-differential CD input that minimizes common mode noise and interference. Each CD signal acts as one side of the differential input and CD_C acts as the other side. CD_C is used as the common return path for both the left and right channels. uses an industry standard Toshiba TOTX-173 optical TOSLINK transmitter.
2.6
CNR Connector and EEPROM
The CNR connector is shown in Figure 7. CNR is a motherboard interface that supports audio, modem, and LAN subsystems. CNR applications are targeted at OEMs, system manufacturers, and system integrators who wish take advantage of physically separating their audio, modem, or LAN circuitry from the PC motherboard. CNR accomplishes this without the additional cost associated with the interface circuitry required for a PCI bus add-in card. The CRD4202-2 uses the AC-Link, SMBus, and power supply pins. The SMBus signals are connected to an AT24C02 EEPROM to provide Plugand-Play functionality for the CNR card. The EEPROM holds the Subsystem Vendor ID and Subsystem ID. It also contains other information for implementing a Plug-and-Play CNR card. For additional information on the CNR design specifications, programming utilities, and information on programming the EEPROM, visit the Intel(R) Communications and Network Riser (CNR) homepage at http://developer.intel.com/technology/cnr/.
2.3
Center, LFE, and Surround Outputs
The audio outputs in Figure 4 drive the rear speakers (surround), center speaker (CNT), and subwoofer (LFE) in six channel applications. These four outputs are driven digitally from the CS4202 through two serial output ports and converted to analog audio through two high-performance CS4334 24-bit stereo DACs.
2.4
Front Channel and Headphone Outputs
Figure 5 details the Headphone and Line Output circuits. The Line Outputs are the main analog outputs in a two channel system, and become the Front Outputs in a six channel audio system. The CS4202 has a built in headphone amplifier on pins 39 and 41. These outputs are capable of driving headphones with impedances as low as 32 . The headphone outputs are AC-coupled through 220 F capacitors. These large capacitor values create excellent low frequency response even under 32 loads.
2.7
Auto Demotion Circuit
The configuration of the codec on the CRD4202-2 will always be set as the primary audio codec in PLL mode. In crystal mode operation it can automatically demote to a secondary codec in the presence of a motherboard codec when R54 is changed to 100 k (Figure 9). This feature is in accordance with the AC '97 Codec Disable and Demotion Rules.
2.5
S/PDIF Optical Output
2.8
Phase Locked Loop
The S/PDIF (IEC-958) digital output shown in Figure 6 is compatible with digital inputs on consumer devices such as Mini Disk recorders and consumer stereo receivers. The S/PDIF output operates at a fixed sampling frequency of 48 kHz. It
4
The CRD4202-2 reference design is configured to operate the CS4202 in Phase Locked Loop (PLL) mode as the primary codec. The external clock must be one of the three supported rates, and the codec ID pins must be properly configured to identify
DS549RD1B1
CRD4202-2
the input clock frequency. Location Y2 in Figure 8 is populated with a 14.31818 MHz surface mounted clock oscillator (test clock) to demonstrate the CS4202 PLL operation. ground plane. Digital components, power traces, and signal traces are not allowed to crossover into the analog section. The CS4202 audio codec is placed at the transition point between the analog and digital ground planes. The analog and digital ground planes must be tied together externally for the CS4202 to maintain proper voltage references. For best results, the two ground planes are tied together with a single 0.050 inch trace under the CS4202 near its digital ground pins. Data converters are generally susceptible to noise on the crystal pins. In order to reduce noise from coupling onto these pins, the area around the 24.576 MHz crystal and its signal traces are filled with copper on the top and bottom of the PCB and attached to digital ground. A separate chassis ground provides a noise-free reference point for all of the EMI suppression components. The chassis ground plane is connected to the analog ground plane at the external jacks.
2.9
Component Selection
Great attention was given to the particular components used on the CRD4202-2 board with cost, performance, and package selection as the most important factors. Listed are some of the guidelines used in the selection of components: * * No components smaller than 0805 SMT package. Only single package passive components. No resistor packs. This reduces the risk of crosstalk between analog audio signals. All components except connectors are in surface mount packages.
*
2.10
EMI Components
Optional capacitors or inductors may be included to help the board meet EMI compliance tests, such as FCC Part 15. Choose these component values according to individual requirements.
3.2
AC-Link
3. GROUNDING AND LAYOUT
The component layout and signal routing of the CRD4202-2 provide a good model for developing new CNR add-in card designs.
3.1
Partitioned Voltage and Ground Planes
It is critical for good audio performance to separate digital and analog sections to prevent digital noise from affecting the performance of the analog circuits. The analog section of the CRD4202-2 is physically isolated from the digital section with a 0.10 inch partition. Partitioning is defined as the absence of copper on all PCB signal layers. The analog and digital sections have their own separate ground planes. All analog components, power traces, and signal traces are routed over the analog
DS549RD1B1
According to the AC '97 revision 2.2 specification, the AC-Link signals can have a maximum capacitance (including traces, connectors, and circuitry) of 47.5 pF on BIT CLK and SDATA_IN (assuming a single codec). If this capacitance is exceeded, timing violations may occur and cause the system to malfunction. In order to avoid adding excessive capacitance, do not add any EMI capacitors to ground on any of the AC-Link lines. In addition, keep the trace length of the AC-Link as short as possible. Keeping the AC-Link trace length under 8 inches is strongly recommend.
3.3
CS4202 Layout Notes
Refer to the CS4202 Data Sheet for analog and digital partitioning guidelines and bypass capacitor placement. Pay special attention to the location of bypass capacitors on REFFLT, AFLT1, AFLT2, and the placement of the power supply capacitors.
5
CRD4202-2
4. REFERENCES
1) Intel(R), Audio Codec '97 Component Specification, Revision 2.2, September, 2000. http://developer.intel.com/ial/scalableplatforms/audio/index.htm/ 2) Intel(R), CNR Specification, Revision 1.1, October 18, 2000. http://developer.intel.com/technology/cnr/ 3) Cirrus Logic, CS4202 Audio Codec '97 Data Sheet http://www.cirrus.com/products 4) Steve Harris, Clif Sanchez, Personal Computer Audio Quality Measurements, Version 1.0 http://www.cirrus.com/pubs/meas100.pdf 5) Microsoft, PC Design Guidelines, http://www.microsoft.com/hwdev/desguid.htm 6) M. Montrose, Printed Circuit Board Design Techniques for EMC Compliance (2nd edition), IEEE Press, New York: 2000.
4.1
* * *
ADDENDUM
Schematic drawings Layout drawings Bill of materials
6
DS549RD1B1
CRD4202-2
ANALOG_IN
LINE_IN_L LINE_IN_R CD_IN_L CD_IN_R CD_C VIDEO_IN_L VIDEO_IN_R AUX_IN_L AUX_IN_R MIC_IN PHONE_IN MONO_OUT PC_BEEP
CS4202
LINE_IN_L LINE_IN_R CD_IN_L CD_IN_R CD_C LINE_OUT_L VIDEO_IN_L VIDEO_IN_R AUX_IN_L AUX_IN_R LINE_OUT_R GPIO2 HP_OUT_L HP_OUT_R HP_OUT_C
ANALOG_OUT
HP_OUT_L HP_OUT_R HP_OUT_C GPIO2 LINE_OUT_L LINE_OUT_R
SPDIF_OUT
MIC1 PHONE_IN MONO_OUT PC_BEEP SPDIF_OUT SPDIF_TX
PLL (optional)
XTAL_IN XTAL_OUT ID0# ID1# XTAL_IN PRIM_DN# XTAL_OUT ID0# ID1# ASDIN ABITCLK ASDOUT SDOUT0 SDOUT1 SCLK LRCLK
SERIAL_PORT
ASYNC SDOUT0 SDOUT1 SCLK LRCLK MCLK
PRIM_SEC_SWITCH
ASDIN PRIM_DN# ASDIN0 ASDIN1
CNR_BUS
PRIM_DN# ABITCLK ASDOUT ASYNC ARST#
ASDIN0 ASDIN1
Figure 1. Block Diagram
DS549RD1B1
ARST#
7
LINE_OUT_R
LINE_OUT_L
MONO_OUT
8
U1 +3.3VD +5VA
25 38 1 9 12
CS4202
26 42 4 7
AVdd1 AVdd2 DVdd1 DVdd2 PC_BEEP PHONE AUX_L AUX_R VIDEO_IN_L VIDEO_IN_R CD_L CD_C CD_R MIC1 MIC2 LINE_IN_L LINE_IN_R Vrefout REFFLT AFLT1 AFLT2 ID0# ID1# XTL_IN XTL_OUT
AVss1 AVss2 DVss1 DVss2 BIT_CLK SDATA_OUT SDATA_IN SYNC RESET# LINE_OUT_L LINE_OUT_R HP_OUT_L HP_OUT_C HP_OUT_R GPIO2 MONO_OUT SPDIF_OUT EAPD/SCLK HPCFG GPIO0/LRCLK GPIO1/SDOUT GPIO3 GPIO4/SDO2
PC_BEEP C1 0.1uF Z5U C2 0.1uF Z5U C3 0.1uF Z5U C4 0.1uF Z5U PHONE_IN AUX_IN_L AUX_IN_R VIDEO_IN_L VIDEO_IN_R CD_IN_L DGND AGND CD_C CD_IN_R MIC1 LINE_IN_L LINE_IN_R
13 14 15 16 17 18 19 20 21 22 23 24 28 27 29 30
R1 5 8 R2 10 11
35 36 39 40 41 32 37 48 47 31 43 44 33 34
6
47 47
ABITCLK ASDOUT ASDIN ASYNC ARST# LINE_OUT_L LINE_OUT_R HP_OUT_L HP_OUT_C HP_OUT_R GPIO2 MONO_OUT SPDIF_OUT SCLK
DGND
AGND
PRIM_DN# C5 2.2uF Y5V C6 0.1uF X7R C7 1000pF NPO C8 1000pF NPO
R55 NO POP
45 46 2 3
LRCLK SDOUT0 SDOUT1
XTAL_IN XTAL_OUT
AGND AGND ID1# ID0#
GND TIE 0.050 inches
For 6 channel Operation, pin 33 is pulled low.
AGND
DGND
Y1
NO POP C13 1000pF NPO
C11 1000pF NPO
C12 1000pF NPO
CRD4202-2
C14 NO POP
C15 NO POP
DS549RD1B1
AGND
DGND
DGND
Figure 2. CS4202 Audio Codec
AGND
DS549RD1B1 9
CD IN
L1 J2 4 3 2 1 31@100MHz C16 1uF ELEC CD_IN_R
LINE IN
J1 4 3 5 2 1 C19 100pF NPO C20 100pF NPO R4 0 C17 1uF ELEC LINE_IN_R
AGND
+
AGND
+
R5
100K
R6
100K
L2
C18
1uF ELEC CD_C
R8
0
C21
1uF ELEC LINE_IN_L
AGND
+
AGND
+
31@100MHz
R9
100K
Connect CGND to AGND at the jack
R10
100K
L3
C22
1uF ELEC CD_IN_L
AGND
+
AGND
CGND
31@100MHz
R12
100K +5VA
VIDEO IN
L4 J4 4 3 2 1 31@100MHz R13 0 C23 1uF ELEC VIDEO_IN_R
MIC IN
J3 4 3 5 2 1 C26 100pF NPO C27 100pF NPO + C28 10uF ELEC R14 2.2K R15 1.5K C24 1uF ELEC MIC_IN
AGND
+
R16
100K
+
L5
R18
0
C25
1uF ELEC VIDEO_IN_L
AGND
+
Connect CGND to AGND at the jack
31@100MHz
R19
100K
AGND
AGND
CGND
AGND
AUX IN
L6 R20 0 C30
BEEP IN
1uF ELEC AUX_IN_R L7 J6 31@100MHz 2 1 L8 R24 0 C33 1uF ELEC AUX_IN_L DGND AGND AGND R23 4.7K C32 2700pF X7R R21 47K C31 0.1uF Z5U PC_BEEP
J5
4 3 2 1 31@100MHz
AGND AGND
+
R22
100K
-3 dB corners at 60 Hz and 13.8 kHz (Ri >= 28 kOhm)
+
31@100MHz
R25
100K
AGND
INTERNAL MODEM CONNECTION
L9 J7 4 3 2 1 31@100MHz R26 0 C34 1uF ELEC PHONE_IN
AGND
+
R27
100K
CRD4202-2
L10
R28
0
C35
1uF ELEC MONO_OUT
+
31@100MHz
R29
47K
AGND
Figure 3. Analog Inputs
SDOUT0
SDATA DEM#/SCLK LRCK MCLK
AOUTR VA+ AGND AOUTL
C37 +
+
SDOUT1 SCLK LRCLK MCLK
SDATA DEM#/SCLK LRCK MCLK
AOUTR VA+ AGND AOUTL
C44 +
+
10
+5VA
SURROUND
U2
1 2 3 4
CS4334 C36
5 7 6 8
JACK
1uF ELEC 1uF ELEC R30 560
4 3 5 2 1
J8
R31
560
Connect CGND
R32 220K +5VA R33 220K R34 47K R35 47K C38 2700pF X7R C39 2700pF X7R
to AGND at the jack
+ C40 10uF ELEC
C41 0.1uF Z5U
C42 0.1uF Z5U AGND AGND CGND AGND
AGND
CNT/LFE
U3
1 2 3 4
CS4334 C43
5 7 6 8
JACK
1uF ELEC 1uF ELEC R36 560
4 3 5 2 1
J9
R37
560
Connect CGND
R38 220K AGND R39 220K R40 47K R41 47K C45 2700pF X7R C46 2700pF X7R
to AGND at the jack
CRD4202-2
AGND
AGND
CGND
AGND
DS549RD1B1
Figure 4. Center Channel, Surround, and Sub-Woofer Outputs
LINE_OUT_R C49 LINE_OUT_L +
+
+
HP_OUT_R C56 HP_OUT_C +
+
DS549RD1B1
GPIO2 HP_OUT_L
LINE OUT JACK
C48 1uF ELEC 1uF ELEC J10
4 3 5 2 1
Connect CGND to AGND at
R44 220K R45 220K C50 100pF NPO C51 100pF NPO
the jack
AGND
CGND +5VA
AGND
R56 10K
HEADPHONE
C54 220uF ELEC 220uF ELEC 1uF ELEC
7 6 2 3 1
JACK
J11
C55
Connect CGND
R48 10K R49 10K C57 100pF NPO C58 100pF NPO
to AGND at the jack
CRD4202-2
AGND
CGND
AGND
AGND
Figure 5. Front Channel and Headphone Sense Output 11
CRD4202-2
SPDIF_TX
J12
5
+5VD
4 3
DGND
R50 C59 0.1uF Z5U
8.2K
2 1 6
TOTX-173 DGND
DGND
Figure 6. S/PDIF Optical Output
12
DS549RD1B1
2
C65 0.1uF Z5U
+ C66 10uF ELEC
GND
DS549RD1B1
+3.3VD C61 0.1uF Z5U + C62 10uF ELEC DGND PRIM_DN# ASYNC ASDOUT ABITCLK TP1 TP2 TP3 DGND +12VD U6
1 IN OUT
P1
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 reserved reserved reserved GND reserved reserved GND LAN_TXD1 LAN_RSTSYNC GND LAN_RXD2 LAN_RXD0 GND reserved +5Vdual USB_OC# GND -12V +3.3VD reserved reserved GND reserved reserved GND LAN_TXD2 LAN_TXD0 GND LAN_CLK LAN_RXD1 reserved USB+ GND USB+12V GND +3.3Vdual +5VD A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
+5VD +12VD C63 0.1uF Z5U + C64 10uF ELEC
B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30
GND EE_DOUT EE_SHCLK GND SMB_A0 SMB_SCL CDC_DN_ENAB# GND AC97_SYNC AC97_SDATA_OUT AC97_BITCLK
GND EE_DIN EE_CS SMB_A1 SMB_A2 SMB_SDA AC97_RESET# AC97_SDATA_IN2 AC97_SDATA_IN1 AC97_SDATA_IN0 GND
A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30
DGND U5
2 3 5 6 A1 A2 SDA SCL A0 WP Vss Vcc
+3.3VD
8
C60
7 4
ARST# ASDIN1 ASDIN0
0.1uF Z5U
1
AT24C02 DGND
CNR Connector TP4 TP5 TP6
DGND
+5VA
3
MC78M05C
+ C67 10uF ELEC
CRD4202-2
DGND
AGND
Connect AGND to DGND with a 50 mil trace near the codec. Connect CGND to DGND with a 50 mil trace near the finger edge of the board.
Figure 7. CNR Connector 13
CRD4202-2
Test Clock Only
XTAL_IN
XTAL_OUT
PLL (Phase Locked Loop)
ID1#
ID0#
For PLL operation:
1) Populate R54 = 1K (Disable MB audio)
+3.3VD R52 NO POP C69 220 pF R53 0
2)
DO NOT populate: Y1, C14, C15, and R55
1
4
R51 2.2K
3
3)
Apply external oscillator to XTAL_IN (pin 2) (CRD4202-2 will use 14.318 MHz test oscillator ECS-8FA3) Populate R51, R52, R53, C68, and C69 according to the desired input clock rate: Clock rate (MHz) 14.31818 24.576 27 48 R51 2.2K R52 R53 C68 C69
C68 .022 uF
4)
2
Y2 14.318 MHz
NO POP 0 ohm
0.022uF 220pF
NO POP NO POP NO POP NO POP NO POP 2.2K 2.2K 0 ohm 0 ohm NO POP 0.022uF 220pF 0 ohm 0.022uF 220pF
DGND
DGND
DGND
Figure 8. Phase Locked Loop
14
DS549RD1B1
CRD4202-2
+3.3VD
R54 = 1K forces motherboard codec(s) to be held in RESET
2 5
R54 1K
U7 TC7SZ125FU
C70 0.1uF X7R
4
ASDIN1
1
PRIM_DN#
3
DGND
+3.3VD
1
ASDIN
2
5
U8 TC7SZ126FU
C71 0.1uF X7R
4
ASDIN0
3
DGND
DO NOT use this circuit for motherboard designs. This circuit is strictly for CNR cards.
For motherboard designs: connect ASDIN to ASDIN0 if primary codec, connect ASDIN to ASDIN1 if secondary codec.
Replace R54 with 100K for automatic demotion when used with primary motherboard codec(s).
Figure 9. Auto Demotion and Serial Buffers
DS549RD1B1
15
CRD4202-2
Figure 10. PCB Layout: Top Assembly Drawing
16
DS549RD1B1
CRD4202-2
Figure 11. PCB Layout: Top Layer
DS549RD1B1
17
CRD4202-2
Figure 12. PCB Layout: Bottom Layer
18
DS549RD1B1
CRD4202-2
Figure 13. PCB Layout: Drill Drawing
DS549RD1B1
19
CRD4202-2
Figure 14. PCB Layout: Top Silkscreen
20
DS549RD1B1
5. BILL OF MATERIALS
Item
1
DS549RD1B1 21
Quantity
12
Reference
C1,C2,C3,C4,C31,C41, C42,C59,C60,C61,C63,C65 C5 C6,C70,C71 C7,C8,C11,C12,C13 C14,C15 C16,C17,C18,C21,C22, C23,C24,C25,C30,C33, C34,C35,C36,C37,C43, C44,C48,C49,C56 C19,C20,C26,C27,C50, C51,C57,C58 C28,C40,C62,C64,C66,C67 C32,C38,C39,C45,C46 C54,C55 C68 C69 J1,J3,J8,J9,J10
Manufacturer
KEMET
Part Number
C0805C104M5UAC
Description
CAP, 0805, Z5U, 0.1 F, 20%, 50V CAP, 1206, Y5V, 2.2 F, 20%, 10V CAP, 0805, X7R, 0.1 F, 10%, 50V CAP, 0805, C0G, 1000 pF, 10%, 50V DO NOT POPULATE CAP, SMT B, ELEC, 1 F, 20%, 50V
2 3 4 5 6
1 3 5 2 19
KEMET KEMET KEMET KEMET PANASONIC
C1206C225M8VAC C0805C104K5RAC C0805C102K5GAC C0805C220K5GAC ECE-V1HA010R
7
8
KEMET
C0805C101J5GAC
CAP, 0805, COG, 100 pF, 5%, 50V
8 9 10 11 12 13
6 5 2 1 1 5
PANASONIC KEMET PANASONIC KEMET KEMET A/D ELECTRONICS MOLEX MOLEX SINGATRON
ECE-V1CA100R C0805C272K5RAC ECE-V0GA221P C805C223K5RAC C805C221K5RAC 3570-50
CAP, SMT B, ELEC, 10 F, 20%, 16V CAP, 0805, X7R, 2700 pF, 10%, 50V CAP, SMT D, ELEC, 220 F, 20%, 4V CAP, 0805, X7R, 0.022 F 10%, 50V CAP, 0805, X7R, 220 pF, 10%, 50V CONN, 1/8" DOUBLE SW. STEREO PHONE JACK
14 15 16
4 1 1
J2,J4,J5,J7 J6 J11
70553-0003 70553-0036 2SJ-09075N53
HDR, 4X1, 0.025" PIN, 0.1" CTR, 15u" AU HDR, 2X1, 0.025" PIN, 0.1" CTR, 150u" SN/PB
CRD4202-2
CONN, 1/8" SINGLE SW. STEREO PHONE JACK W/INSULATOR CONN, OPTICAL TOSLINK TRANSMITTER IND, FBEAD, 1206, 31@100MHz, 25%
17 18
1 10
J12 L1,L2,L3,L4,L5,L6,L7,L8, L9,L10
TOSHIBA TDK
TOTX173 HF50ACB321611-T
22 DS549RD1B1
19 20 21
1 2 9
P1 R2,R1 R4,R8,R13,R18,R20,R24, R26,R28,R53 R5,R6,R9,R10,R12,R16, R19,R22,R25,R27 R14,R51 R15 R21,R29,R34,R35,R40,R41 R23 R30,R31,R36,R37 R32,R33,R38,R39,R44,R45 R48,R49,R56 R50 R52,R55 R54 TP1,TP2,TP3,TP4,TP5,TP6 U1
NONE PHILIPS PHILIPS
NONE 9C08052A47R0J 9C08052A0R00J
CNR BUS CONNECTOR RES, SO, 0805, 47, 5%, 1/10W, METAL FILM RES, SO, 0805, 0, 5%, 1/10W, METAL FILM
22
10
PHILIPS
9C08052A1003J
RES, SO, 0805, 100K, 5%, 1/10W, METAL FILM
23 24 25 26 27 28 29 30 31 32 33 34
2 1 6 1 4 6 3 1 2 1 6 1
PHILIPS PHILIPS PHILIPS PHILIPS PHILIPS PHILIPS PHILIPS PHILIPS PHILIPS PHILIPS KEYSTONE Cirrus Logic
9C08052A2201J 9C08052A1501J 9C08052A4702J 9C08052A4701J 9C08052A5600J 9C08052A2203J 9C08052A1002J 9C08052A8201J 9C08052A0R00J 9C08052A1001J 5015 CS4202-JQ
RES, SO, 0805, 2.2K, 5%, 1/10W, METAL FILM RES, SO, 0805, 1.5K, 5%, 1/10W, METAL FILM RES, SO, 0805, 47K, 5%, 1/10W, METAL FILM RES, SO, 0805, 4.7K, 5%, 1/10W, METAL FILM RES, SO, 0805, 560, 5%, 1/10W, METAL FILM RES, SO, 0805, 220K, 5%, 1/10W, METAL FILM RES, SO, 0805, 10K, 5%, 1/10W, METAL FILM RES, SO, 0805, 8.2K, 5%, 1/10W, METAL FILM DO NOT POPULATE RES, SO, 0805, 1K, 5%, 1/10W, METAL FILM MINI SMT TEST POINT IC, TQFP, AC '97 2.2 SERIAL CODEC W/ HP AMP + SRC IC, SO, SOIC8, STEREO DAC, 24 BITS IC, SO, SOIC8, SERIAL EEPROM, 256 x 8, 2.7V IC, SO, +5V REGULATOR, DPAK, 4%, 500mA
35 36 37 38 39 40 41
2 1 1 1 1 1 1
U2,U3 U5 U6 U7 U8 Y1 Y2
Cirrus Logic ATMEL MOTOROLA TOSHIBA TOSHIBA FOX ECS
CS4334-KS AT24C02N-10SC-2.7 MC78M05CDT TC7SZ125FU TC7SZ126FU FS24.576 ECS-8FA3
CRD4202-2
IC, SSOP5-P-0.65A, single 3 state buffer, 2.6ns IC, SSOP5-P-0.65A, single 3 state buffer, 2.6ns DO NOT POPULATE Clock OSC, 14.31818MHz, SMT
* Notes *

▲Up To Search▲

Price & Availability of CRD4202-2

	To Download CRD4202-2 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .